1) Field of the Invention
This invention relates generally to the field of semiconductor processing, and more particularly, to reduction of electromigration and stress voids in metal interconnect structures.
2) Description of the Prior Art
The ever increasing requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron-sized, low resistance-capacitance (RC) metallization patterns. Conventional semiconductor devices typically comprise a semiconductor substrate, usually a doped monocrystalline silicon (Si), and plurality of sequentially formed interlayer dielectrics and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by inter-wiring spacings. Typically, the conductive patterns of vertically spaced metallization layers are electrically connected by vertically oriented conductive plugs filling via holes formed in the interlayer dielectric layer separating the metallization layers, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and micro-miniaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization layers is known as “damascene”—type processing. Generally, this processing involves forming an opening (or via) in the dielectric interlayer, which will subsequently separate the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After the opening is formed, the opening is filled with conductive material, such as tungsten or copper, using conventional techniques. Excess conductive material on the surface of the dielectric interlayer is then typically removed by chemical mechanical planarization (CMP).
High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization layers. Copper and copper-based alloy metallization systems have very low resistivities, which are significantly lower than tungsten and even lower than those of previously preferred systems utilizing aluminum and its alloys. Additionally, copper has a higher resistance to electromigration. Furthermore, copper and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver and gold. Also, in contrast to aluminum and refractory-type metals, copper and its alloys can be readily deposited at low temperatures formed by well-known (wet) plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with requirements of manufacturing throughput.
The more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 6,633,085—Besser, et al.—shows a method of selectively alloying interconnect regions by ion implantation. A metal interconnect structure and method of making the same implants ions of an alloy elements into a copper line through a via. Then ion implantation of the alloy elements in the copper line through the via provides improved electromigration properties at the copper line at a critical electromigration failure site, without attempting to provide alloy elements throughout the entire copper line.
U.S. Pat. No. 6,500,749—Liu, et al.—Method to improve copper via electromigration (EM) resistance—Ions are implanted through the via pattern hole into the metal via portion, and any portion of the metal interconnect structure above the metal via portion. Whereby the metals have improved electromigration resistance.
U.S. Pat. No. 6,713,875—Farrar—Barrier layer associated with a conductor layer in damascene structures.
US 20030160330 A1—McTeer, Allen—Copper interconnect for an integrated circuit and method for its fabrication—A small dose of titanium is implanted in the copper surface. The implanted titanium layer suppresses the copper oxide growth in the copper bond pad by controlling the concentration of vacancies available to the copper ion transport.
U.S. Pat. No. 6,426,289—Farrar—shows a method of fabricating a barrier layer associated with a conductor layer in damascene structures.
U.S. Pat. No. 6,117,770—Pramanick, et al. shows a method for implanting semiconductor conductive layers.
U.S. Pat. No. 6,228,759—Wang, et al. shows a method of forming an alloy precipitate to surround interconnect to minimize electromigration. An alloy precipitate is formed to surround a conductive fill within an interconnect opening, including especially a top surface of the conductive fill. The alloy precipitate at the top surface and at the grain boundary of the conductive fill prevents drift of the conductive material along the top surface and along the grain boundary of the conductive fill and into the insulating layer surrounding the interconnect opening.
US 20040005773 A1—Lopatin,; et al.—Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect—A method of fabricating an integrated circuit includes forming a barrier layer along lateral side walls and a bottom of a via aperture and providing a ternary copper alloy via material in the via aperture to form a via.